Line Coding (8B/10B)

Digital data is fundamentally a stream of binary bits (0s and 1s), but transmitting it over physical media — copper wire, optical fiber, and so on — requires converting those bits into electrical or optical signals. This conversion involves far more than simply mapping bit values to voltage levels.

Two of the most significant challenges are DC component accumulation and receiver clock synchronization. When the same bit value repeats for an extended period (e.g., a long run of 00000... or 11111...), the voltage remains at one polarity and a DC component builds up in the signal.

Furthermore, with no signal transitions occurring, the Phase-Locked Loop (PLL) circuit at the receiver loses its ability to extract a clock, making it impossible to identify the boundaries between data bits. These issues seriously compromise the reliability and integrity of data transmission.

Line coding was developed to address these fundamental problems. It refers to the set of rules used to convert digital data into a digital signal suitable for a given physical transmission medium, including the inverse decoding rules. The goal of line coding is not merely to transform data, but to reduce signal distortion, enable error detection, and optimize the signal for the characteristics of the channel — most importantly, to solve the clock synchronization problem.

Clock Synchronization

In high-speed serial communication, transmitting data and clock signals on separate wires is inefficient. Most systems instead adopt self-clocking, embedding clock information directly within the data stream. The receiver detects signal transitions (High-to-Low or Low-to-High changes) and uses a PLL to recover the clock. However, if the same voltage level persists for an extended period — as in 11111... or 00000... — no transitions occur, and the receiver’s PLL loses its timing reference. This prevents the receiver from distinguishing the start and end of individual bits, ultimately leading to data loss and loss of synchronization. Line coding solves this by deliberately introducing transition-inducing patterns, guaranteeing that a signal change will occur within a defined interval regardless of how long a run of identical bits lasts.

0000000000... ────────────────  (no edges!)
CDR:  ? ? ? ? ? ?               (can't lock!)

DC Component Elimination

Digital signals represent 0 and 1 through specific voltage levels. A long run of 1s sustains a positive voltage, while a long run of 0s sustains a near-zero or negative voltage. This sustained single-polarity condition is known as a DC component. Many communication channels cannot pass DC components — for example, transformer-coupled Ethernet channels and the automatic gain control (AGC) circuits in optical receivers are sensitive to DC offsets. As the DC component accumulates, the average signal voltage drifts away from zero, introducing signal distortion and errors. Line coding achieves DC balance by keeping the number of transmitted 0s and 1s approximately equal, holding the long-term average voltage close to zero.

Data 0xFF: ──────────  (all 1s → DC offset)
Data 0x00: ──────────  (all 0s → DC offset)

AC-coupled link:  ──||──  capacitor blocks DC
                        → baseline drift → bit errors

Overview of Common Line Coding Schemes

The simplest line coding scheme, NRZ (Non-Return-to-Zero), maps 1 to a positive voltage and 0 to zero or a negative voltage. However, NRZ suffers severely from both synchronization loss and DC accumulation during long runs of identical bits. To address these issues, Manchester encoding was introduced. Manchester coding forces a signal transition at the midpoint of every bit period, completely solving the clock synchronization problem. However, because it uses two signal events per bit, it carries 100% overhead, doubling the required bandwidth relative to the actual data rate.

The Context of Technical Evolution

Manchester coding effectively addressed DC components and clock synchronization, but at the cost of bandwidth efficiency. Its 100% overhead was acceptable in low-speed environments but became a serious bottleneck as communication speeds entered the gigabit era. Transmitting 1 Gbps of data over Manchester encoding requires a 2 Gbps signal rate.

This inefficiency created a new design constraint: as data rates increased, Manchester’s 100% overhead became unsustainable, driving the need for new line coding schemes that could preserve essential functionality while dramatically reducing overhead. The answer to this need was block coding schemes such as 8B/10B. By processing data in blocks, 8B/10B achieves far greater efficiency than Manchester encoding while still guaranteeing DC balance and clock recovery.

Fundamentals and Structure of 8B/10B

8B/10B encoding was first described by IBM’s Al Widmer and Peter Franaszek in 1983. As the name suggests, it converts 8-bit data into 10-bit symbols — a block coding technique. This introduces 2 bits of overhead per symbol, representing a 20% bandwidth penalty. Compared to Manchester’s 100% overhead, however, this is a dramatic improvement in efficiency.

8B/10B splits an 8-bit input (HGF EDCBA) into its lower 5 bits (EDCBA) and upper 3 bits (HGF), processing each through separate 5b/6b and 3b/4b encoding stages. The results are combined to form the final 10-bit symbol (abcdei fghj). This subdivided encoding structure provides the foundation for the fine-grained Running Disparity management mechanism described below.

Input  (8-bit): H G F E D C B A
                └─┬─┘ └───┬───┘
                 3B(MSB) 5B(LSB)
                        ↓
Output (10-bit): a b c d e i | f g h j   ← wire order (LSB group first)
                 └────6B────┘  └──4B──┘

Core Principle A: DC Balance via Running Disparity (RD)

The most distinctive and important feature of 8B/10B is its dynamic DC balance management through a concept called Running Disparity (RD). Disparity refers to the difference between the number of 1s and 0s in a given bit sequence; Running Disparity tracks the cumulative disparity accumulated across the entire transmitted bit stream.

The key insight of 8B/10B is that for some 8-bit inputs, the encoding provides two alternative 10-bit output symbols with different numbers of 1s and 0s. The encoder checks the current Running Disparity value to decide which alternative to use.

Running Disparity Rules:

• If the previous RD is positive (+1), select the symbol with more 0s to reduce the overall RD.
• If the previous RD is negative (-1), select the symbol with more 1s to increase the overall RD.
• If the symbol has equal numbers of 1s and 0s, the RD remains unchanged.

Thanks to this dynamic selection mechanism, the long-term ratio of transmitted 1s and 0s is kept close to 50%, achieving DC balance with the average signal voltage converging to zero. In 8B/10B systems, the initial RD is set to negative (-1), and the running disparity state always toggles between +1 and -1 (binary state), not the absolute sum. The disparity of each individual symbol is limited to ±2.

Symbol Disparity Example

Symbol disparity is the difference between the number of 1s and 0s in a codeword (symbol):

101101 → four 1s, two 0s → disparity = +2
010010 → two 1s, four 0s → disparity = −2
101010 → three 1s, three 0s → disparity = 0

Running Disparity (RD) Example

As symbols are transmitted, the cumulative difference between 1s and 0s is tracked as the running disparity:

Transmitted symbols: 101101  →  010010  →  101010  →  101101
Symbol disparity:      +2         −2           0         +2
Cumulative sum:        +2          0           0         +2
RD state:             (+)         (−)         (−)        (+)

RD only tracks the direction: “Have more 1s (+) or more 0s (−) accumulated so far?” The absolute value is not tracked, only the sign.

The terms RD = -1 and RD = +1 are conventional labels, not the actual cumulative disparity value. Sometimes called “positive running disparity” and “negative running disparity.”

flowchart TD
  inputRD --> encode5b6b --> mid[Intermediate RD after 5b/6b]
  mid --> encode3b4b --> finalRD

After 5b/6b encoding, the disparity may change, and the updated RD is passed to the 3b/4b encoding stage.

Example: K28.5

Core Principle B: Bounded Disparity and Run Length Limiting

Bounded Disparity means that the absolute value of the Running Disparity never exceeds a defined limit (±2 in 8B/10B). This property ensures long-term DC balance.

Additionally, 8B/10B limits the number of consecutive identical bits to no more than 5. This rule directly guarantees the signal transitions needed by the receiver’s PLL to recover the clock. By capping the run length at 5, 8B/10B ensures that a signal transition will always occur within a fixed interval, regardless of the data content, effectively preventing clock synchronization loss.

The Role and Significance of Control Symbols (K Codes)

Beyond the 256 data symbols (D codes), 8B/10B defines 12 special control symbols (K codes). K codes follow different encoding rules from D codes and are used to perform link-layer control functions outside of normal data transmission — for example, signaling the start and end of frames, the idle state of the link, or skip sequences.

Certain K codes, notably K.28.5, are called comma symbols and are used for synchronization: they define symbol boundaries within the bit stream. K.28.5 contains a run of five consecutive identical bits within its 10-bit symbol. This specific pattern never appears spanning the boundary between any two valid symbols, which means the receiver can lock onto a symbol boundary from any arbitrary position in the bit stream. K.28.7 shares the same comma property but carries a disparity of ±4, making it a burden on DC balance when used alone — which is why K.28.5 is the more commonly used comma. The receiver detects this comma pattern to precisely identify the start and end of each 10-bit symbol.

Technical Value and System-Level Significance

8B/10B encoding is not simply a bit-expansion technique. It is a carefully engineered solution that strategically invests 20% overhead to simultaneously solve DC balance and clock recovery. Running Disparity is the specific dynamic control mechanism that achieves the goal of DC balance, made possible by providing two alternative encodings for symbols with unequal numbers of 1s and 0s. This demonstrates that line coding design involves not just simple transformation but sophisticated control through dynamic state management.

Furthermore, the existence of K codes reveals that 8B/10B is not merely a physical-layer data conversion technology — it is deeply involved in the frame structure and state management of the data link layer above it. By enabling precise identification of frame boundaries within the data stream via comma symbols, 8B/10B maximizes receiver synchronization reliability, showing that it contributes to overall system stability well beyond the hardware signal integrity concerns it was originally designed to address.

<8B/10B Encoding Conversion Rules and Running Disparity (RD) Example>

The table below illustrates the Running Disparity management rules of 8B/10B. The input symbol D.21.5 has equal numbers of 0s and 1s (disparity = 0), so it uses the same encoding regardless of the current RD state. K.28.5 is a K code whose 10-bit symbol contains a run of five consecutive identical bits followed by two different bits, allowing the receiver to detect symbol boundaries.

Comparison with 64B/66B and Next-Generation Coding Schemes

8B/10B’s 20% overhead was effective at 1 Gbps, but became a serious bottleneck as communication speeds exceeded 10 Gbps. At 100 Gbps, a 20% overhead translates to a 20 Gbps bandwidth loss — an unacceptable penalty. To overcome this limitation, next-generation schemes such as 64B/66B and 128B/130B were developed.

64B/66B encoding adds a 2-bit header (01 or 10) to a 64-bit data block, yielding an extremely low overhead of approximately 3%. The header’s sole function is to distinguish data blocks from control blocks. Unlike 8B/10B, 64B/66B does not directly transform data to achieve DC balance; instead, it relies on a separate technique called scrambling. Scrambling pseudo-randomizes the data to minimize the likelihood of long runs of identical bits, providing an efficient alternative solution to both DC components and run-length issues.

8B/10B Encoding Table References

8B/10B Valid Characters • Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) • Reader • AMD Technical Information Portal

Appendix A: 8b/10b and 10b/8b Encoding Tables | GlobalSpec

Next: The Role of Scrambling in High-Speed Serial Communication