https://docs.amd.com/r/2021.1-English/ug949-vivado-design-methodology/When-and-Where-to-Use-a-Reset

Advantages of Synchronous Resets

BenefitExplanationBetter Resource MappingSynchronous resets can be mapped directly to more FPGA resources (e.g., flip-flops inside DSPs, BRAMs).Improved Logic PerformanceAsynchronous resets can negatively affect general logic timing paths and increase routing complexity.Simpler RoutingA global asynchronous reset might not increase control sets but does require routing reset wires to many elements, which can become complex.Protects Memory StructuresAsynchronous resets may corrupt the contents of BRAMs, LUTRAMs, and SRLs during reset assertion—especially if those resources are driven by asynchronously reset registers.Placement FlexibilityWith synchronous resets, the logic can be more easily remapped during implementation for better packing and performance.Compatibility with Dedicated BlocksSome blocks like DSP48s and BRAMs only support synchronous resets, so using asynchronous resets can prevent proper inference into those blocks.

Reset HDL Coding Example

Changing Asynchronous Reset into Synchronous Reset on Multipiler

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// Asynchronous reset: may prevent inference into DSP48 internal registers
always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    p <= 0;
  else
    p <= a * b;
end

// Synchronous reset: matches the reset structure supported by DSP blocks
always @(posedge clk) begin
  if (!rst_n)
    p <= 0;
  else
    p <= a * b;
end

Commenting Out Code with Reset Conditions

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always @(posedge clk) begin
  if (!rst_n) begin
    valid <= 1'b0;
    // data  <= 16'd0;  // Do not reset data-path registers
  end else begin
    valid <= next_valid;
    data  <= next_data;
  end
end

Separate Procedural Statements for Registers With and Without Reset

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// Reset only registers whose initial value matters, such as control signals
always @(posedge clk) begin
  if (!rst_n)
    valid <= 1'b0;
  else
    valid <= next_valid;
end

// Put data-path registers in a separate always block without reset
always @(posedge clk) begin
  data <= next_data;
end

The Optimal way to remove the resets is to create separate sequential logic procedures with one for reset condition and the other for non-reset conditions.

Summary: In FPGAs…

ItemRecommended?Reason✅ Synchronous resetCommonly recommendedBetter for timing, tool support⚠️ Asynchronous resetUse with cautionNeeded for power-up init, but adds complexity✅ Active-low resetPreferredMore immune to noise, widely adopted standard✅ Active-high resetAcceptableLogically fine, but less common in industry