Line Coding (8B/10B)

Digital data is fundamentally a stream of binary bits (0s and 1s), but transmitting it over physical media — copper wire, optical fiber, and so on — requires converting those bits into electrical or optical signals. This conversion involves far more than simply mapping bit values to voltage levels. Two of the most significant challenges are DC component accumulation and receiver clock synchronization. When the same bit value repeats for an extended period (e.g., a long run of 00000... or 11111...), the voltage remains at one polarity and a DC component builds up in the signal. ...

August 21, 2025 · 10 min · EasyFPGA

From Parallel Bus to High-Speed SERDES and Gigabit Transceivers

The Limits of Parallel Buses Traditional parallel data buses were efficient at low clock rates, but as clock frequencies increased they ran into fundamental physical barriers. The core problem is timing skew: with many parallel data lanes plus a separate clock lane, each signal travels a slightly different path length on the PCB and through the package, arriving at the receiver at slightly different times. As the clock period shrinks, even a small skew becomes a significant fraction of a bit period, and data errors follow. ...

August 21, 2025 · 4 min · EasyFPGA

High Speed Serial Communication with AMD's Gigabit Transceiver

What is the High Speed Serial Communication? High-speed serial communication is a method of transmitting data bit by bit over a single or multiple lanes at very high speeds. It is widely used in modern computing, networking, and embedded systems due to its efficiency and scalability 1 Gbps - 10 Gbps → Used in Gigabit Ethernet (1000BASE-X), PCIe Gen1/2, SATA, USB 3.0 10 Gbps - 25 Gbps → Found in 10GBASE-R Ethernet, PCIe Gen3, Fibre Channel ...

June 5, 2025 · 3 min · EasyFPGA