SystemVerilog

Custom RTL Design: TX & RX This is the first hands-on RTL episode. We translate the UART protocol specification directly into synthesizable SystemVerilog — starting from the mathematical relationship between clock frequency and baud rate, then building the TX FSM and RX center-sampling logic. Each design decision is derived from first principles so you can reproduce and modify it for any FPGA or baud rate. Design Requirements Target: 50 MHz system clock, 8E1 format ...

CRC (Cyclic Redundancy Check) is the most widely used error-detection mechanism in digital communication — from Ethernet frames to USB packets to SSD data integrity. This post explains how CRC works mathematically and shows how to use the free online CRC Calculator & RTL Generator to produce ready-to-simulate SystemVerilog code for your FPGA design. What Is CRC? CRC appends a checksum to a data block so the receiver can detect corruption. The transmitter computes a CRC value over the data and appends it; the receiver recomputes the CRC and compares. A mismatch means a transmission error occurred. ...

What Is a Critical Path? The critical path is the longest combinational logic path between any two registers in a synchronous digital circuit — measured in propagation delay. It sets a hard lower bound on your clock period: $$T_{clk} \geq T_{critical_path} + T_{setup} + T_{hold}$$ $$F_{max} = \frac{1}{T_{clk}}$$ Everything else in your design can run faster. The critical path is the single bottleneck that caps the maximum clock frequency. A Concrete Example 1 2 3 4 // Bad: long critical path always_ff @(posedge clk) begin result <= a + b + c + d + e + f + g + h; // 7 chained additions end What happens in a single clock cycle: ...